1. Field of the Invention
The present invention relates to a light emitting display device in which a light emitting element constituting a pixel is actively driven by a TFT (Thin Film Transistor) and particularly to an active type light emitting display device in which a problem occurring in the case where a so-called threshold voltage compensation technique is utilized as a lighting driving means for a light emitting element can be solved.
2. Description of the Related Art
A display using a display panel in which light emitting elements are arranged in a matrix pattern has been developed widely. As a light emitting element employed in such display panel, an organic EL (electro-luminescent) element in which an organic material is employed in a light emitting layer has attracted attention. This is because of backgrounds one of which is that by employing, in a light emitting layer of an EL element, an organic compound which enables an excellent light emitting characteristic to be expected, a high efficiency and a long life have been achieved which make an EL element satisfactorily practicable.
As display panels in which such organic EL elements are employed, a simple matrix type display panel in which EL elements are simply arranged in a matrix pattern and an active matrix type display panel in which an active element consisting of a TFT is added to each of EL elements arranged in a matrix pattern have been proposed. The latter active matrix type display panel can realize low power consumption, compared to the former simple matrix type display panel, and has characteristics such as less cross talk between pixels and the like, thereby being specifically suitable for a high definition display constituting a large screen.
FIG. 1 shows a most basic circuit configuration corresponding to one pixel 10 in a conventional active matrix type display device, which is called a conductance control technique. In FIG. 1, a gate of a controlling TFT (Tr1) comprised of P-channels is connected to a scan line extending from a scan driver 1, and its source is connected to a data line extending from a data driver 2. A drain of the controlling TFT (Tr1) is connected to a gate of a driving TFT (Tr2) comprised similarly of P-channels and to one terminal of a capacitor C1 provided for holding electrical charges.
A source of the driving TFT (Tr2) is connected to the other terminal of the capacitor C1 and to an anode side power source (VHanod) supplying a driving current to an EL element E1 provided as a light emitting element. A drain of the driving TFT (Tr2) is connected to an anode of the EL element FL1, and a cathode of this EL element is connected to a cathode side power source (VLcath).
When an ON controlling voltage (Select) is supplied to the gate of the controlling TFT (Tr1) shown in FIG. 1 via the scanline, the controlling TFT (Tr1) allows current which matches a data voltage (Vdata) supplied from the data line to the source to flow from the source to the drain. Therefore, during the period when the gate of the controlling TFT (Tr1) is ON voltage, the capacitor C1 is charged, and the capacitor's voltage is supplied to the gate of the driving TFT (Tr2). Thus, the driving TFT (Tr2) allows current which is based on the gate voltage and the source voltage of the TFT (Tr2) to flow in the EL element E1 to drive the EL element so that the EL element emits light.
When the gate of the controlling TFT (Tr1) becomes an OFF voltage, the controlling TFT (Tr1) becomes a so-called cutoff, and the drain of the controlling TFT (Tr1) becomes an open state. The gate voltage of the driving TFT (Tr2) is maintained by electrical charges accumulated in the capacitor C1, the driving current is maintained until a next scan, and the light emission of the EL element 14 is also maintained.
Meanwhile, in order to actively drive a current drive type light emitting element represented by an organic EL element, it is remarked that a material constituting a TFT has to have a considerably high electron mobility, and in general a low temperature polysilicon is employed in order to drive the light emitting element. However, in this type of polysilicon TFT, it is know that threshold voltage variations occur due to formation of a crystal body, and these threshold voltage variations of TFTs causes variations in drain currents of driving TFTs. It is known that the above-mentioned organic EL element emits light whose intensity is approximately proportional to the driving current, and thus the drain current variations of driving TFTs directly cause light emission intensity variations among pixels.
Thus, in order to compensate unevenness in intensity among pixels based on variations in threshold voltages of TFTs, a pixel structure provided with four TFTs as shown in FIG. 2 has been proposed. The structure shown in FIG. 2 is called a threshold voltage compensation technique herein, and by this structure, operation is performed so as to effectively compensate the threshold characteristic of a driving TFT as described later. This threshold voltage compensation technique is introduced in Reference 1 shown below which is not a patent document:
Sang-Hoon Jung, Woo-Jin Nam and Min-Koo Han, “A New Voltage Modulated AMOLED Pixel Design Compensating Threshold Variation of Poly-Si TFTs,” SDI International Symp. Proc., pp. 622–624, 2002.
In the structure of FIG. 2, a gate of a controlling TFT (Tr1) comprised of P-channels is connected to a scan line extending from a scan driver 1, and its source is connected to a data line extending from a data driver 2. A drain of the controlling TFT (Tr1) is similarly connected to a gate of a driving TFT (Tr2) of P-channel type via a parallel connection part of P-channel type TFT (Tr3), TFT (Tr4) formed in the same pixel 10.
A capacitor C1 which maintains the gate voltage of the driving TFT (Tr2) in a lighting driving state of an EL element E1 is connected between the gate and the source of the driving TFT (Tr2), and said source is connected to an anode side power source (VHanod) which supplies a driving current to the EL element E1. The drain of the driving TFT (Tr2) is connected to an anode of the EL element E1, and a cathode of this EL element is connected to a cathode side power source (VLcath).
The parallel connection part of the TFT (Tr3) and the TFT (Tr4) connected between the drain of the controlling TFT (Tr1) and the gate of the driving TFT (Tr2) is constructed in such a way that respective gates and drains are in a short circuit state and that the sources and the gates of the TFT (Tr3) and the TFT (Tr4) are connected in reverse parallel.
In the above-described structure, the roles of the controlling TFT (Tr1), the driving TFT (Tr2), and the electrical charge holding capacitor C1 are approximately similar to those in the example shown in FIG. 1. In the structure in which the sources and the gates of the TFT (Tr3) and the TFT (Tr4) are connected in reverse parallel, when the electrical potential (Va=Vdata) of a point in FIG. 2 is a predetermined value higher than the electrical potential (Vb) of b point, the TFT (Tr3) is brought to an ON state, and the TFT (Tr4) is brought to an OFF state. Conversely, when the electrical potential (Va) of a point is a predetermined value lower than the electrical potential (Vb) of b point, the TFT (Tr3) is brought to an OFF state, and the TFT (Tr4) is brought to an ON state. Utilizing these functions, in the pixel structure shown in FIG. 2, for example, performed are a reset operation in which the electrical charges of the capacitor C1 are reset for every frame and a write operation in which data is newly written in the capacitor C1.
FIG. 3 is timing charts for explaining such operations, and first, at a timing shown as 1, a Select voltage supplied from the scan driver 1 is switched to a low level. By this, the controlling TFT (Tr1) is brought to the ON state. At this time data voltage Vdata supplied from the data driver 2 is at a low level, thus the TFT (Tr4) is bought to the ON state, and a terminal voltage of the capacitor C1, that is, the electrical potential of b point (Vb), is reset to a state of a fully low in the vicinity of the above-described low level Vdata.
Then, at a timing shown as 2, the data voltage Vdata supplied from the data driver 2 is raised. At this time the TFT (Tr3) becomes the ON state, and the TFT (Tr4) is brought to the OFF state. Accordingly, a data voltage whose level is dropped a threshold voltage caused by the TFT (Tr3) from the data voltage Vdata supplied from the data driver 2 (that is, a data voltage which is level shifted to a lower voltage side) is written in the capacitor C1 as the gate voltage.
Thereafter, at a timing shown as 3, since the Select voltage supplied from the scan driver 1 is switched to a high level, the controlling TFT (Tr1) is brought to a cutoff state, and at a timing shown as 4, the data voltage Vdata is switched to the low level. That is, it can be stated that the period from said 1 to said 2 is a reset period and that the period from said 2 to said 3 is a data writing period with respect to the capacitor C1. Based on the driving TFT (Tr2) gate voltage which has been written in the capacitor C1 in the writing period, the driving TFT (Tr2) supplies the driving current (drain current) to the EL element E1 over a period of one frame.
Therefore, a part between the source and the gate of the TFT (Tr3) functions as a threshold voltage generating element by which a level shift is performed using the threshold voltage, and a part between the source and the gate of the TFT (Tr4) functions as a reset element by which the terminal voltage of the capacitor C1 is reset and becomes a predetermined voltage through the ON operation of the TFT (Tr4).
Meanwhile, variations in the threshold voltages of the respective TFT (Tr2) and TFT (Tr3) formed in the same pixel as shown in FIG. 2 is considerably small, and it can be stated that both threshold voltages are almost the same. Accordingly, in the writing period, the gate voltage written in the capacitor C1 is allowed to be a value obtained by canceling the threshold voltage of the driving TFT (Tr2) substantially. Thus, the drain current of the driving TFT (Tr2) which drives the EL element E1 by electrical charges of the capacitor C1 is not dependent upon its threshold voltage, and as a result, the light emission intensity of the EL element E1 is not affected by variation of the threshold voltage of the driving TFT.
Accordingly, in the case where the pixel structure by the threshold voltage compensation technique shown in FIG. 2 is adopted, influence due to variations in threshold voltages of driving TFTs can be reduced effectively without particularly adding something such as a control line or the like to a light emitting display panel and without making a peripheral driving circuit complex.
With the structure shown in FIG. 2 in which the threshold voltage compensation technique is adopted, in the reset period in which the gate voltage accumulated in the capacitor C1 is reset, the terminal voltage of the capacitor C1, that is, the electrical potential of b point (Vb), is reset to the state of the fully low in the vicinity of the low level of Vdata via the controlling TFT (Tr1) and the portion between the gate and the source of TFT (Tr4) which functions as the reset element. Thus, with the structure shown in FIG. 2, the data voltage Vdata of the low level is applied similarly to the gate of the driving TFT (Tr2). Therefore, the driving TFT (Tr2) fully becomes the ON state (turn on state), though it is momentary, so as to allow a large amount of driving current (excess current) to flow in the EL element via the driving TFT (Tr2).
Under the influence of this, in the display panel, deterioration of contrast, deterioration of linearity in a low gradation, and the like occur, and problems, such as a problem that the life of a light emitting element is shortened, occur. In the example shown in FIG. 2, although the TFTs, all of which are of a P-channel type, are used, even when an N-channel type is employed for the respective TFTs, excess current momentarily flows in the EL element accompanied by the reset period similarly, and thus problems similar to the above problems occur.